The present invention relates to controlling inrush current in a power supply, and more particularly, to circuitry for controlling inrush current efficiently during cold startup, warm startup and power line disturbance conditions.
The control of inrush current is especially important in N+1 redundant power systems. If excessive inrush current blows a fuse or trips the main circuit breaker on an AC distribution board, then the redundancy of the entire system is lost, even if the power supply is still functioning properly. The inrush current requirements of modem power supplies are very stringent, demanding efficient control of inrush current even during abnormal power line disturbances and for high current applications.
To control inrush current, conventional methods may employ a relay, thermistor, thyristor or similar switch, often in combination with a resistor or thermistor, in an attempt to limit inrush current in an AC-DC power supply. As is known in the art, a thermistor is a component with a resistance that decreases as its temperature increases. During power supply startup, the temperature of the thermistor is cold and its resistance high, a characteristic that can be used to limit inrush current. As the power supply continues to operate, the temperature increases and the resistance of the thermistor decreases, thereby allowing more current during normal operation.
FIG. 1 illustrates a prior art method and circuit disclosed in U.S. Pat. No. 5,202,819 to Min that includes a thermistor for controlling inrush current. Although the disclosed method provides inrush current control, it has major drawbacks. One drawback is that a Thermistor TH1 in smoothing circuit 3 is always present as a series element, resulting in power dissipation proportional to the input current. This method is therefore inefficient especially for high current applications. In addition, if a power line disturbance (PLD) occurs during operation, the hot thermistor will be functioning at low resistance and so will not limit inrush current effectively. Thus, to prevent inrush current caused by the PLD, some delay must be built in to first allow the thermistor to cool or a circuit provided that bypasses the thermistor, in order to control inrush current.
Another drawback of the prior art circuit shown in FIG. 1 is that it uses a xe2x80x9cNear Zero Crossingxe2x80x9d detection for triggering two silicon controlled rectifiers (SCRs) in the phase control rectifying circuit 5. An SCR is a device which is normally non-conducting, with conduction initiated by application of a gate current. The SCR will remain ON (i.e., conducting) until current flowing in the SCR is reduced to some minimum level. If AC power fails at a non zero phase angle, slightly higher than sensed for xe2x80x9cNear Zero Crossingxe2x80x9d, and recovers at the same angle after a period of one cycle, the control circuit 4 in FIG. 1 will wait for the next near zero crossing, after nearly another half AC cycle, before triggering the SCRs. A larger bulk capacitor C2 will be required to provide energy during such a power line disturbance, even when AC is restored. The result is a circuit that costs more and that has increased space requirements.
FIG. 1A shows a timing diagram that illustrates this drawback of the prior art circuit of FIG. 1. The SCR drive signal waveform shows the SCR gate drive pulses that occur at near zero phase angle. When AC fails at a non-zero phase angle, as shown in the Rectified Pulses waveform at point A, the SCR gate drive signal will stay ON as long as energy is available on C2. If C2 has too much energy, however, there is a possibility that, due to circuit delays, the SCRs will trigger when AC restores at point B. This would result in heavy inrush current. If the charge on C2 decays, then the SCR""s gate drive is unavailable at point B for nearly one half cycle, upon restoration of AC power, until another zero crossing occurs at point C. As mentioned above, this problem forces use of a bigger bulk capacitor to maintain charge during the hold up period.
Another prior art method of inrush current control is disclosed in U.S. Pat. No. 5,715,154 to Rault, and shown in FIG. 2. This method has a drawback of including an extra series switch, Thyristor, TH. This extra switch will dissipate additional power; the dissipation being proportional to the input current. Thus, this method has the drawback of being very inefficient, especially for higher power applications, resulting in higher cost and the need for space-consuming heat sinking due to the increased dissipation.
FIG. 3 illustrates another conventional circuit for inrush current control. The circuit of FIG. 3 provides some inrush current control but has the drawback of not providing control during power line disturbance conditions. Modem power supply applications demand controlled inrush current even during power line disturbances that result in lost AC power. At power start up, both SCR1 and SCR2 in the bridge rectifier shown in FIG. 3 are in the OFF state due to a lack of gate drive voltage. The initial inrush current flows through elements D1, D2, R1, and D5 into a bulk capacitor Co at the output of the circuit. The amount of inrush current can be kept below a desired value by choosing an appropriate value for limiting resistor R1. In operation, the Power Factor Control (PFC) boost regulator PFC1 then starts operating by drawing power through D1, D2, and R1. Bias voltage is induced in the secondary winding on the boost choke L due to the switching action of the boost switch Q1. This induced bias voltage drives the SCRs. At that point, all power is delivered through the diode-SCR bridge.
Although the circuit of FIG. 3 can control inrush current satisfactorily for hot or cold start up conditions, the circuit has the drawback of not providing the inrush current control demanded by current generation power supplies when power line disturbances occur. Assuming an operating condition when a DC-DC converter (not shown) coupled to the output is already active and drawing power from the PFC boost regulator PFC1 at a low line voltage, e.g., 90V AC. If a power line disturbance occurs causing a missing AC cycle, bulk capacitor Co at the output can continue to deliver power to the DC-DC converter during this xe2x80x9chold upxe2x80x9d period. If capacitor C1 is small and cannot hold sufficient charge for driving the SCRs during this hold up period, and if AC is restored in a time interval slightly less than the hold up time; then PFC 1 will start switching immediately through D1, D2, and RI with most of the voltage dropped in R1. This will require a longer time to generate the required gate drive for the SCRs, which results in depletion of the charge on Co. Alternatively, if C1 is made sufficiently large, the depletion problem can be solved, as the SCRs will remain ON and can then support the required power levels of the DC-DC converter. The circuit of FIG. 3 does, however, have the drawback of not controlling inrush current at high line voltage during a power line disturbance condition. If an AC cycle is missed in a high line voltage condition, Co will deliver the hold up power and the voltage across it will drop accordingly. In this case, the SCRs are kept ON due to the charge available on C1. Under this condition, restoration of AC at the 90-degree phase angle and peak of 264V AC results in an undesirably huge inrush current. Thus, under power line disturbance conditions, the conventional method and circuit in FIG. 3 does not control inrush current satisfactorily.
What is needed is a reliable and efficient circuit and corresponding method for controlling inrush current in high-power electronic power supplies during hot and cold startup conditions and during power line disturbances.
The present invention solves the problems of prior art devices by providing a circuit and corresponding method which provides control to limit inrush current during cold startup, hot startup and power line disturbance conditions in AC to DC converters. The circuit of the present invention can be used for AC to DC converters with active power factor correction circuitry. The circuit includes a logic circuit that operates such that whenever AC is lost, SCR gates are turned OFF and are allowed to turn ON only when AC is restored and the instantaneous AC voltage is less than the bulk voltage at the time, thus eliminating the possibility of undesirable heavy inrush current. The circuit can also be used for non-power factor corrected applications if an auxiliary high side drive bias is available for the SCRs used in the bridge rectifier.
Broadly stated, the present invention provides a method of controlling inrush current in a AC-DC converter when AC power is lost during power line disturbance conditions comprising the steps of maintaining a plurality of SCRs in an OFF state to limit inrush current when the AC power is lost; comparing the instantaneous AC input voltage to the DC output voltage of the converter; comparing the instantaneous AC input voltage to a predetermined voltage level; and triggering the plurality of SCRs to the ON state only when the AC power is restored to the predetermined level and the instantaneous input AC voltage is less than the DC voltage at the output of the AC-DC converter. In addition, broadly stated, the present invention provides a circuit for providing control of inrush current in an AC to DC power converter during power disturbance conditions, wherein the AC to DC converter includes two input terminals to which AC power is coupled and two output terminals where the output DC power is provided, comprising a bridge rectifying circuit including a plurality of SCRs; a circuit to provide a drive bias for the plurality of SCRs; an output capacitor connected across the output terminals of the converter; a control circuit for controlling the rectifying circuit to limit inrush current, the control circuit being operatively connected to the gate inputs of the plurality of SCRs; and means for comparing the AC input and DC output voltages of the converter for causing the plurality of SCRs to enter a conduction state when the AC input voltage exceeds a predetermined threshold and the AC input voltage is less than the DC output voltage.
Consequently, the circuit and corresponding method of the present invention have the advantage that inrush current is controlled both for hot startup and cold startup conditions.
Another advantage of the present invention is full control of inrush current even during power line disturbance conditions.
Still another advantage of the present invention is that there is no need for an extra series dissipative device, and its consequent additional losses.